
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity OEM_Interface_testbench is
end OEM_Interface_testbench;

architecture I2Cwrite of OEM_Interface_testbench is

  component I2CmasterDemo_mybuf is
    Port ( FPGA_Clk : IN std_logic;
		       I2C_Clk : out std_logic;
    		     I2C_Data : inout std_logic;
    	   	  SW : IN std_logic_vector(3 downto 0);
				   IMG_RST : out std_logic;
				   DataToSend : in std_logic_vector(15 downto 0));
  end component;
  
  component slave_interface is
  --component OEM_Interface is
        Port(IMG0_I2C_Clk : out std_logic;
	         		IMG0_I2C_Data : out std_logic;
			       IMG0_Data : in std_logic_vector(9 downto 0);
			       IMG0_PIXEL_Clk : in std_logic;
			       IMG0_ROW_EN : in std_logic;
			       IMG0_VSYNC : in std_logic;
			       IMG0_RST : out std_logic;
			
			       IMG1_I2C_Clk : out std_logic;
			       IMG1_I2C_Data : out std_logic;
			       IMG1_Data : in std_logic_vector(9 downto 0);
			       IMG1_PIXEL_Clk : in std_logic;
			       IMG1_ROW_EN : in std_logic;
			       IMG1_VSYNC : in std_logic;
			       IMG1_RST : out std_logic;
			
			       OEM_I2C_Clk : inout std_logic;
			       OEM_I2C_Data : inout std_logic;
			       OEM_Data : out std_logic_vector(9 downto 0);
			       OEM_PIXEL_Clk : out std_logic;
			       OEM_ROW_EN : out std_logic;
			       OEM_VSYNC : out std_logic;
			
			       Clk_100MHz : in std_logic;
			
	     				  SW : in std_logic_vector(3 downto 0);
	     				  LED : out std_logic_vector(3 downto 0)
             );
  end component;
  
  signal fpgaclk,i2cclk,i2cdata,rst : std_logic:='0';
  signal sw : std_logic_vector(3 downto 0):="0000";
  
  signal rid : std_logic_vector(7 downto 0);
  signal dts,dout,master_dts : std_logic_vector(15 downto 0);
  signal dir : std_logic;
  
  signal sIMG0_I2C_Clk,sIMG0_I2C_Data : std_logic;
  signal sIMG0_Data : std_logic_vector(9 downto 0);
  signal sIMG0_PIXEL_Clk,sIMG0_ROW_EN,sIMG0_VSYNC,sIMG0_RST,sIMG1_I2C_Clk,sIMG1_I2C_Data : std_logic;
  signal sIMG1_Data : std_logic_vector(9 downto 0);
  signal sIMG1_PIXEL_Clk,sIMG1_ROW_EN,sIMG1_VSYNC,sIMG1_RST,sOEM_I2C_Clk,sOEM_I2C_Data : std_logic;
  signal sOEM_Data : std_logic_vector(9 downto 0);
  signal sOEM_PIXEL_Clk,sOEM_ROW_EN,sOEM_VSYNC,sClk_100MHz : std_logic;
  signal sSW,sLED : std_logic_vector(3 downto 0);
begin
  
  fpgaclk<=not fpgaclk after 10 ns;
  
  Master: I2CmasterDemo_mybuf port map(fpgaclk,i2cclk,i2cdata,sw,rst,master_dts);
  
  slave: slave_interface port map (
  --FPGA_interface: OEM_Interface port map(
       sIMG0_I2C_Clk,
     		sIMG0_I2C_Data,
       sIMG0_Data,
       sIMG0_PIXEL_Clk,
       sIMG0_ROW_EN,
       sIMG0_VSYNC,
       sIMG0_RST,
  
       sIMG1_I2C_Clk,
       sIMG1_I2C_Data,
       sIMG1_Data,
       sIMG1_PIXEL_Clk,
       sIMG1_ROW_EN,
       sIMG1_VSYNC,
       sIMG1_RST,
  
       i2cclk,
       i2cdata,
       sOEM_Data,
       sOEM_PIXEL_Clk,
       sOEM_ROW_EN,
       sOEM_VSYNC,
  
       fpgaclk,
  
			 sSW,
   			 sLED
  );
  
  process
  begin
    master_dts<=X"0001";
    wait for 100 us;
    sw<="1000";
    wait for 100 us;
    sw<="0000";
    wait for 200 us;
    master_dts<=X"0000";
    sw<="1000";
    wait;
  end process;
end I2Cwrite;
